A memory controller within a computer can be designed to run synchronously or asynchronously with the local bus associated with the central processing unit (CPU). The problem with running the memory controller asynchronously with the bus is that the overall system performance is not as good, bus control signal synchronization delays are present and interaction with the bus is oftentimes not as predictable.
Accordingly, it is desirable to be able to operate the memory controller synchronously with the local bus in the computer. In so doing, since the speed associated with various performance characteristics of the computer are enhanced and because the signals are synchronous, the interaction with the bus is more predictable.
Furthermore, it is desirable to be able to stop the local bus clock associated with the CPU and its local bus as a power-saving feature while at the same time the memory controller continues to display an image. In laptops, notebook and portable computers this power saving feature, known as sleep mode, is very important to extending the battery life of the computer. In so doing, the memory controller runs on the local bus clock and must be active to execute memory cycles to refresh the display and refresh the frame buffer memory associated with the computer.
A known solution to this problem has been to provide a separate local bus clock that continued running while the computer is in the sleep mode. However, this scheme is undesirable because a separate local bus clock would have a skew from the clock that the processor uses, which would reduce how quickly the frame memory could be accessed. The additional clock would therefore reduce reliability and would also require additional clock generation circuitry. As has been above mentioned, this additional circuitry would be undesirable because it would consume additional power.
Accordingly, what is needed is a memory controller system which can operate synchronously with the local bus clock but when in a sleep mode doesn't require the additional circuitry and additional unreliability associated with providing a separate local bus clock. The present invention addresses such a need.